Smc-networks ARM PL241 Manuel d'utilisateur télécharger pdf (Page 86)

Programmer’s Model for Test

4.1 SMC integration test registers

Test registers are provided for integration testing.

Figure 4-1 shows the SMC integration test register map.

Figure 4-1 SMC integration test register map

Table 4-1 lists the SMC integration test registers.

4.1.1 SMC Integration Configuration Register at 0x1E00

The read/write smc_int_cfg Register selects the integration test registers. This register

is only for test. This register cannot be read or written to in the Reset state.

Figure 4-2 shows the register bit assignments.

Figure 4-2 smc_int_cfg Register bit assignments

VPFBLQWBRXWSXWV

VPFBLQWBLQSXWV

VPFBLQWBFIJ

[(

[(

[(

Table 4-1 SMC test register summary

Name

Base

offset

Type

Reset

value

Description

smc_int_cfg

0x1E00

R/W

0x0

SMC Integration Configuration Register at 0x1E00

smc_int_inputs

0x1E04

RO - Integration Inputs Register at 0x1E04 on page 4-3

smc_int_outputs

0x1E08

WO - Integration Outputs Register at 0x1E08 on page 4-4

 

LQWBWHVWBHQ

8QGHILQHG

1 2 ... 81 82 83 84 85 86 87 88 89 90 91 ... 109 110

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Smc-networks ARM PL241 Manuel d'utilisateur Page 86