Smc-networks ARM PL241 Manuel d'utilisateur télécharger pdf (Page 44)

Functional Overview

Direct commands

The SMC enables code to be executed from the memory while simultaneously, from the

software perspective, moving the same chip to a different operating mode. This is

achieved by synchronizing the update of the chip configuration registers from the

holding registers with the dispatch of the memory configuration register write.

The SMC provides two mechanisms for simultaneously updating the controller and

memory configuration registers.

Device pin mechanism

For memories that use an input pin to indicate that a write is

intended for the configuration register, for example in some

PSRAM devices, the write mechanism can be done through the

APB direct command register. Figure 2-12 on page 2-25 shows

the sequence of events.

Software mechanism

For memories that require a sequence of read and write

commands, for example, most NOR Flash devices use the SMC

interface, with the write data bus indicating when the last transfer

has completed and when it is safe for the SMC to update the chip

configuration registers. Figure 2-13 on page 2-26 shows the

sequence of events.

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Smc-networks ARM PL241 Manuel d'utilisateur Page 44