Smc-networks ARM PL241 Manuel d'utilisateur télécharger pdf (Page 58)

Functional Overview

Figure 2-23 Synchronous read and asynchronous write

Programming t

and t

when the controller operates in synchronous mode

For t

• when using memory devices that are not wait-enabled, you must program t

be the number of clock cycles required before valid data is available following the

assertion of cs_n

• when using memory devices that are wait-enabled, you must program t

to be

the number of clock cycles required before wait is active and stable, following the

assertion of cs_n. That is:

t_RC = 3 + t_CEOE

Note

t_CEOE is only required if wait is asserted when oe_n goes LOW.

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Smc-networks ARM PL241 Manuel d'utilisateur Page 58