Smc-networks ARM PL241 Manuel d'utilisateur télécharger pdf (Page 51)

Functional Overview

Asynchronous write in multiplexed-mode

Table 2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings.

Figure 2-17 shows an asynchronous write in multiplexed-mode. t

is seven cycles. t

is four cycles, and is extended by two cycles for the address phase of the transaction.

Figure 2-17 Asynchronous write in multiplexed-mode

Asynchronous page mode read

Table 2-10 and Table 2-11 list the smc_opmode0_<0-3> and SRAM Register settings.

Table 2-8 Asynchronous write in multiplexed-mode opmode chip register settings

Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba

Value - - - b0 b000b0b0--

Table 2-9 Asynchronous write in multiplexed-mode SRAM cycles register settings

Field t_rc t_wc t_ceoe t_wp t_pc t_tr

Value - b0111 - b100 - -

VPFBPFON

VPFBFVBQB>@

VPFBDGYBQB

VPFBGDWDBHQB

VPFBZHBQB

VPFBGDWDBRXWB>@





Table 2-10 Page read opmode chip register settings

Field mw rd_sync rd_bl wr_sync wr_bl baa adv bls ba

Value - b0 <page length> - - - - - b1

Table 2-11 Page read SRAM cycles register settings

Field t_rc t_wc t_ceoe t_wp t_pc t_tr

Value b0011 - b010 - b001 -

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 109 110

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Smc-networks ARM PL241 Manuel d'utilisateur Page 51